- New Camera, Physical Layer and Low-Latency Interfaces Meet Market Demands
BARCELONA, Spain, Feb. 27, 2013 /PRNewswire/ -- MOBILE WORLD CONGRESS -- MIPI Alliance today announced the next generation of three specifications designed to dramatically improve chip-to-chip interface communication in mobile devices. CSI-3 provides higher bandwidth over fewer pins with better power per bit efficiency than CSI-2. The low latency memory-mapped LLI v2.0 is a functional upgrade adding features such as improved link efficiency and link power management, as well as reduced link electromagnetic interference (EMI). M-PHY® v3.0 delivers a low-power, scalable physical layer with a data rate range nearing 6Gbps. CSI-3 has been adopted and is available for MIPI Alliance members. LLI v2.0 and M-PHY® v3.0 are scheduled for adoption by the end of April 2013. For more information, visit MIPI Alliance at Mobile World Congress Hall 8.1, Stand E46 or go to www.mipi.org [http://www.mipi.org/]
In addition to supporting smartphones and full-function phones, these MIPI specifications are suitable for other applications that require low power, high bandwidth - including tablets/netbooks, consumer electronics, high speed memory storage, automotive and portable medical devices.
"While all of our specifications are developed within mobile device parameters, we know that mobile functionality is expanding to other applications," said Joel Huloux, Chairman of the Board of MIPI Alliance. "MIPI specifications are best-in-class when considering low-power, high bandwidth chip-to-chip communication."
CSI-3 Provides Smaller, More Power-Efficient Interconnect CSI-3 is a new generation of camera serial interface. It addresses the integration of camera subsystems such as RAW image sensors, SOC cameras, Image Signal Processors (ISP) and bridge devices with a host processor such as an application processor. CSI-3 is based on the high-speed serial M-PHY physical layer on the UniPro(SM) protocol. The combination of these two entities, also known as UniPort-M, plus the improved functionality of the camera interface provides higher bandwidth over fewer pins, with better power per bit efficiency than the previous specification. In addition, CSI-3 is optical friendly, providing mobile product designers with an optional low-complexity electro-optical signal conversion and transport for additional assembly and reliability benefits.
LLI v2.0 Improves Power Management and Link Efficiency The Low Latency Interface (LLI v1.0, LLI v2.0) is a point-to-point interconnect between the application processor and modem/baseband/companion processor. Using this high bandwidth interconnect enables the baseband processor to access the application processor's dedicated DRAM memory for baseband processor operation, thus eliminating a separate, dedicated DRAM chip and saving cost and board space. LLI v2.0 is backwards compatible with LLI v1.0 and supports all use-cases such as remote chip cache re-fills. LLI v2.0 enhances the support of attaching a companion chip to the main SoC. This includes a definition of a new frame format, improving the link efficiency and power management features of the combined system. LLI v2.0 defines a scrambling function which mitigates the EMI on the link. In addition, LLI v2.0 provides in-built support for IPC Protocol that helps easier system integration.
M-PHY GEAR 3 Delivers Key Features M-PHY v3.0 is a high bandwidth serial interface with an exceptionally wide data rate range spanning 10kbps to near 6Gbps. Bandwidth can be scaled based on the application needs, by selecting from several available transmission rates or by scaling up to multiple transmission lanes, making M-PHY a very flexible physical layer. Multiple transmission modes plus a low energy per bit threshold rate equals significant power efficiency.
The M-PHY physical layer has been adopted as the transport of choice for the SuperSpeed USB Inter-Chip (SSIC) specification, JEDEC's Universal Flash Storage (UFS) specification v1.1, and the upcoming M-PCIe® specification, an adaptation of the PCI Express® (PCIe®) architecture.
About MIPI Alliance
MIPI Alliance is a global, collaborative organization comprised of companies that span the mobile ecosystem and are committed to defining and promoting interface specifications for mobile devices. MIPI Specifications establish standards for hardware and software interfaces which drive new technology and enable faster deployment of new features and services.
MIPI® and M-PHY® are registered marks of MIPI Alliance, Inc.
CONTACT: Marcia Barnett, +1-214-868-8861, email@example.com
Web site: http://www.mipi.org/